Practical Low Power Digital Vlsi Design Pdf Download

CMOS technology is now the dominant technology in digital circuits. When this book was published, CMOS technology was pushing the limits of digital circuit design. The circuit complexity of CMOS technology is far more than is needed for most digital designs. Designers are forced to make a variety of trade-offs to get most of their designs to work. The cost of designing a circuit in CMOS often translates to a high manufacturing cost. The CMOS technology is also subject to failure under several major failure mechanisms. CMOS failures are cumulative and can easily lead to functional failures. The biggest failures are the static failures. These static failures are most often due to the properties of the CMOS technology. The CMOS technology is an active analog circuit technology that is typically implemented as NMOS and PMOS transistors. Due to the historical bias that favors p-type devices in the transistors, the CMOS technology exhibits a strong p-type conduction. The CMOS technology is an inherently good switch and can easily be turned on or off by the voltage applied to the gate terminal. Unfortunately, this voltage control also means that the state of the device will not be stable. It is easily turned on and off by noise from other devices or random events. The state of the device may change immediately or may remain in the wrong state for long periods of time. In addition, once the CMOS device is turned on, it is very difficult to turn it off. The static effect on the CMOS device is readily apparent on power supplies, fuses and EPROM's. These devices exhibit a gradual decrease in resistance as the voltage is turned off. The analog nature of the CMOS technology also causes glitches at power on (turn on) and power off (turn off) which can be a major reliability problem. The small amount of capacitance between the gate and drain terminal of a CMOS device creates several reliability issues. The turn on and off of CMOS devices creates a large amount of gate-to-drain capacitance. The stored gate-to-drain charge can be several hundred volts or more. This can lead to large voltage spikes that are applied to the gate of the CMOS devices. The large amount of capacitance can also cause very high current spikes.

The following is a quick tutorial on the basic background of low power VLSI design. (C) 1992, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 by the authors. All rights reserved. All other marks are the property of their respective owners.

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